Reducing Compilation Time of Zhong's FPGA-Based SAT Solver
نویسندگان
چکیده
We present schemes to reduce the compilation time of conngurable hardware that solves Boolean Satiss-ability. The SAT solver presented by Zhong in last year's FCCM conference has a large compilation time overhead mainly due to placement and routing of many FPGAs. We attack the problem on 3 fronts. First, we partitioning the SAT solver into instance-speciic and instance non-speciic components. Secondly, we transform SAT instances to a canonical form; and nally we present a board-level architecture to solve large SAT instances. All these eeorts amount to a reduction in placement and routing time to conngure the conngurable hardware. We are able to reduce the compilation time to mere routing time of the implication circuits for each instance of the SAT problem, given the best scenario.
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